1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In power semiconductors such as vertical insulated-gate Field Effect Transistors (FETs) like “metal-oxide-semiconductor (MOS) FETs”, a current flows between an electrode at a top surface of a semiconductor substrate and an electrode at a bottom surface of the semiconductor substrate, and ON/OFF is controlled by a MOS structure formed in the upper surface side. For example, in the case of a vertical MOS device, when a current flows and the device turns “ON”, the current passes through the electrode at the top surface, a channel region, a drift layer, and the bottom-surface electrode. Therefore, a loss according to electric resistance of each component occurs. In addition, in the case where the device includes a Junction Field Effect Transistor (JFET) region in order to establish a high breakdown voltage, as the electric resistance further increases, the loss further increases. As one of methods of reducing such a loss, a method of reducing a resistance component of a drift layer by thinning a semiconductor substrate is known.
Herein, the factor of determining the breakdown voltage are roughly an electric-field intensity applied to the device, specific resistivity of the semiconductor substrate, and a thickness of the semiconductor substrate. The electric-field intensity is controlled by being designed so that the electric-field intensity is equal to or smaller than a value of dielectric breakdown strength depending on a material of the semiconductor substrate. For example, the dielectric breakdown strength of silicon (Si) is 0.3 MV/cm, and in order to achieve a breakdown voltage of 1200 V, a thickness of about 120 micrometers is required. The specific resistivity of the semiconductor substrate is controlled by adjusting a concentration of impurities doped into the semiconductor substrate. In addition, the thickness of the semiconductor device roughly depends on the thickness of the drift layer.
Therefore, in the case where a structure for suppressing extension of a depletion layer by a field stop layer or the like is introduced, or in the case where a desired breakdown voltage is lower, the semiconductor substrate can be further thinned to reduce the resistance component of the drift layer, but a mechanical strength of the semiconductor substrate itself is reduced. As a method for solving the above problem, for making the semiconductor substrate thin under a state where the mechanical strength of the semiconductor substrate is enhanced, a scheme of grinding the bottom surface portion of the semiconductor substrate is known. The scheme of grinding is conducted under a state such that the semiconductor substrate is bonded to a plate different from the semiconductor substrate at an upper surface side of the semiconductor substrate in which the device structure is provided. Here, the plate different from the semiconductor substrate serves as a supporting-substrate.
However, in the case of wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C), problems different from the case of Si occurs. For example, the dielectric breakdown strength of 4H—SiC is 2.8 MV/cm, which is about ten times larger than the dielectric breakdown strength of Si. Therefore, while achieving a higher breakdown voltage corresponding to the level of the breakdown voltage of Si, a thickness required for the semiconductor substrate of SiC may be about one-tenth ( 1/10) of the thickness of Si. For example, even at a breakdown voltage of 1200 V, the required thickness is only about ten micrometers.
Therefore, SiC is advantageous because the resistance component can be made smaller than the resistance component of Si and the loss of the device can be reduced by thinning the drift layer of the semiconductor substrate. However, if the thickness becomes extremely thin as about ten micrometers, because the mechanical strength of the semiconductor substrate of SiC becomes extremely low, various problems occur under the state where the supporting-substrate on the top surface is removed, after the thinning process.
For example, a high possibility such that the semiconductor substrate might be broken due to deformation ascribable to the stress caused by dicing process, or due to stress deformation when a diced chip is joined to a dicing tape or the like exists. In addition, deformation or the like brought by a thick adhesive of the dicing tape will cause a high possibility that the semiconductor substrate might be broken after the joining process.
In addition, if the semiconductor substrate is extremely thin, the treatment of a single chip will produce a high possibility that the chip might be easily broken due to internal stress caused by a change in the device structure, or by a temperature change, or alternatively, due to external stress ascribable to the treatment of the single chip or connection with wirings, or the like.
Even in the case where a supporting-substrate is attached to the top surface of the semiconductor substrate, if the semiconductor substrate is extremely thin, there is a high possibility that the semiconductor substrate might be damaged by an impact at the time of detaching the supporting-substrate from the semiconductor substrate. As described above, there is a problem such that the handling difficulty of the chips greatly increases as the thickness of the wide bandgap semiconductor becomes extremely thin, because the mechanical strength is greatly lowered.
In view of a method for reinforcing the mechanical strength of the semiconductor device, WO 2010/140666A discloses a method using a reinforcement ring in the outer periphery of the bottom surface of a semiconductor substrate, or of the bottom surface of a wafer. In addition, JP 2010-251632A discloses a method of providing a reinforcement glass on a device-side surface of the semiconductor substrate. However, in the methods of WO 2010/140666A and JP 2010-251632A, although the mechanical strength of the semiconductor substrate before dicing can be mechanical strengthened, because the reinforcement ring or the reinforcement glass is removed in the dicing process of the chips, the mechanical strength as individual chips cannot be enhanced, and handling the chips after dicing is hard.
In addition, JP 2010-529646A discloses a method for selectively removing portions of the substrate to intentionally leave thick regions of the substrate in the chip state. However, the SiC is a material which is relatively hard to process, and in the case of the method of JP 2010-529646A, a problem exists such that much time and cost are required for the manufacturing works.
In addition, JP 2002-076326A discloses a method which use one of two Si substrates as a rib on a bottom-surface of the other Si substrate, after direct-bonding the two Si substrates. However, in JP 2002-076326A, a SiC substrate is not considered. For manufacturing a SiC device, thermal processes are performed at a high temperature of about 1600° C. or more so as to enable SiC epitaxial growth and impurity doping into SiC.
On the other hand, the melting point of Si is about 1414° C., which is lower than 1600° C. In JP 2002-076326A, since the melting point of Si is not considered, when the Si substrate is used as the rib of the SiC substrate as it is, the Si substrate cannot withstand the process temperature of the SiC epitaxial growth and the impurity doping into SiC. Therefore, a SiC device that can be used actually cannot be manufactured by JP 2002-076326A.
In addition, JP 2003-282845A discloses a method of bonding two substrates through an oxide film. However, in order to manufacture a vertical semiconductor device, removing the oxide film at a bonding surface is necessary, but detailed description associated with removing process of the oxide film is not clearly disclosed in JP 2003-282845A. In addition, although the description that the oxide film becomes an etch stopper is recited in JP 2003-282845A, a process of removing an unnecessary oxide film after stop of etching is not described.
Therefore, in the case of JP 2003-282845A, manufacturing a vertical semiconductor device is actually difficult. In addition, when the oxide film at the bonding interface is removed by etching, a problem of lowering of the bonding-strength between the two substrates occurs, because the remove of the etchant, which has been intruded into the bonding interface during etching, is very difficult.